1. Field of the Invention
The present invention relates to a bias circuit. More particularly, it relates to a bias circuit for an emitter coupled logic (ECL) circuit in a large scale integrated circuit (LSI) which can be driven at a relatively low power-supply voltage for the purpose of suppressing heat generation therein.
Generally, in bipolar-type logic circuits such as ECL circuits, the delay time for one logic circuit stage depends largely on the amount of current flowing through the circuit. That is, the delay time in each circuit is inversely proportional to the amount of current flowing therethrough as long as the parasitic capacitances in the circuit, the wiring capacitances of the wires for connecting elements in the circuit, the switching capability of each transistor in the circuit, and the ratio of currents delivered to various elements in the circuit, are constant. In other words, the greater the current supplied to the circuit, the higher the switching speed. Because of this, when trying to decrease the power consumption of integrated circuits, it is better to lower the power supply voltage rather than the current. Reduction of the power consumption of integrated circuits is necessary from the viewpoint of decreasing the amount of heat generated in the circuits, which is one of the factors limiting the degree of integration. The more power consumption in a circuit, the more heat is generated. The power consumption in each gate is especially great in conventional bipolar-type integrated circuits.
Two power supplies are generally used for an ECL integrated circuit, i.e., a power supply for providing a voltage of -5.2 V through -4.5 V to the circuit and a power supply for providing a voltage of -2 V as a terminating voltage at the ends of signal lines. The bias circuit according to the present invention aims to be operated at the voltage of -2 V which is regularly used for the termination of signal lines in ECL circuit systems.
2. Description of the Prior Art
FIG. 1 is a diagram of a conventional bias circuit and a conventional ECL circuit to which a bias voltage is applied. In the figure, the ECL circuit ECL.sub.0 consists of input transistors T.sub.1 and T.sub.2, a reference transistor T.sub.3, a transistor T.sub.4 functioning as a constant current source, an output transistor T.sub.5 for outputting a logical NOR output X.sub.0, an output transistor T.sub.6 for outputting a logical OR output X.sub.0, load resistors R.sub.1 and R.sub.2, and resistors R.sub.3, R.sub.4, and R.sub.5, for current feedback, connected to the emitters of the transistors T.sub.4, T.sub.5, and T.sub.6, respectively. To the base of the reference transistor T.sub.3, a first bias voltage V.sub.BB0, output from a bias circuit BC.sub.0, is applied. To the base of the transistor T.sub.4, a second bias voltage V.sub.CS0, output from the bias circuit BC.sub.0, is applied.
The bias circuit BC.sub.0 consists of resistors R.sub.6 and R.sub.7 diodes D.sub.1 and D.sub.2, and a resistor R.sub.8 connected in series between a first power supply terminal V.sub.CC and a second power supply terminal V.sub.EE0. The bias circuit BC.sub.0 also consists of transistor T.sub.7 and T.sub.8 and a resistor R.sub.9 connected in series between the first power supply terminal V.sub.CC and the second power supply terminal V.sub.EE0. The base of the transistor T.sub.7 is connected to a connecting point between the resistors R.sub.6 and R.sub.7. The base of the transistor T.sub.8 is connected to a connecting point between the resistor R.sub.7 and the diode D.sub.1.
The first bias voltage V.sub.BB0 is determined by the base-emitter voltage V.sub.BET of the transistor T.sub.7, which is about 0.8 V, and the voltage drop across the resistor R.sub.6, which is, for example 0.5 V. Therefore, the voltage V.sub.BB0 is about -1.3 V. The bias voltage V.sub.BB0 is higher than a low level (L level) of, for example, -1.7 V and lower than a high level (H level) of, for example, -0.9 V.
The operation of the ECL circuit ECL.sub.0 is well known. In brief, when at least one of the inputs A.sub.0 and B.sub.0 is at the H level, the transistor T.sub.1 or T.sub.2 is on, or both transistors T.sub.1 and T.sub.2 are on, and the transistor T.sub.3 is off, resulting, at the NOR output X.sub.0, in the L level of about -1.7 V, which is determined by the voltage drop (0.9 V) across the resistor R.sub.1 and the base-emitter voltage (0.9 V) of the transistor T.sub.5. At the OR output X.sub.0, the H level of about -0.9 V results which is determined by the base-emitter voltage (0.8 V) of the transistor T.sub.6 and the voltage drop (0.1 V) across the resistor R.sub.2. The L level voltage at the output X.sub.0 or X.sub.0 is partially determined by the ratio of the resistors R.sub.1 and R.sub.3. When both of the inputs A.sub.0 and B.sub.0 are at the L level, the transistors T.sub.1 and T.sub.2 are both off, and the transistor T.sub.3 is on, resulting in the H level at the NOR output X.sub.0 and resulting in the L level at the OR output X.sub.0.
Generally, in an ECL circuit, the first power supply voltage (also referred to as V.sub.CC) is 0 V, and the second power supply voltage (also referred to as V.sub.EE1) is a negative voltage. In order to suppress the generation of heat in the ECL circuit, it is desirable to limit the voltage difference between V.sub.CC and V.sub.EE0 as much as possible. However, when the conventional bias circuit BC.sub.0 is employed, the minimum voltage difference between V.sub.CC and V.sub.EE0 for reliable operation is about 3 V, as explained in the following. That is, the voltage difference between V.sub.CC and V.sub.EE0 is determined by the sum of the voltage drops across the resistor R.sub.6, the base-emitter voltage of the transistor T.sub.7, the base-collector voltage of the transistor T.sub.8, the forward bias voltages across the diodes D.sub.1 and D.sub.2, and the voltage drop across the resistor R.sub.8. The maximum collector-base voltage of the transistor T.sub.8, for keeping its collector-base junction in a reverse bias state in order to prevent the transistor T.sub.8 from being operated in a saturation region, is 0 V. The base-emitter voltage of each transistor and the forward bias voltage of each diode, when manufactured of silicon, are both about 0.8 V. Therefore, the voltage difference between V.sub.CC and V.sub.EE0 should be at least 2.4 V. In order to attain stable operation, the voltage drops across the resistors R.sub.6 and R.sub.8 should be, for example, about 0.2 V and 0.4 V, respectively. As a result, the above-mentioned sum is about 3 V. Therefore, the second power supply V.sub.EE0 should be lower than -3 V. The absolute value of this voltage is too great for increased integration in an integrated circuit.
In the conventional circuit of FIG. 1, if the second power supply voltage V.sub.EE0 is -2 V, the base-emitter voltage of the transistor T.sub.7 and the forward bias voltage of the diodes D.sub.1 and D.sub.2 would become insufficient, thereby preventing operation of the bias circuit BC.sub.0.